The present invention relates to non-volatile memory systems. More particularly, the present invention relates to methods of data management in non-volatile memory systems.
Flash memory is widely used in computers, memory cards, and the like. As the use of portable information devices such as cellular phones, PDA, digital cameras, and the like has become more widespread in recent years, flash memories have been used as a storage device to replace traditional hard disks. The above-described mobile devices may require mass storage devices in order to provide various functions (e.g., to record and/or playback full motion video). To satisfy such requirements, multi-bit memory devices have been developed which store 2 or more data bits in one memory cell. A memory cell storing multi-bit data may be called a Multi-Level Cell (MLC), whereas a memory cell storing 1-bit data may be called a Single-Level Cell (SLC). In the case of a flash memory device adopting an MLC configuration, the usable capacity may be increased, while the time taken to write data may also be increased. In contrast, in a flash memory device adopting an SLC configuration, the usable capacity may be relatively low as compared to an MLC flash memory device, while the time taken to write data may be relatively short as compared to an MLC flash memory device. That is, a flash memory device adopting the SLC configuration may operate at a relatively high speed as compared with a flash memory device adopting the MLC configuration. Further, hybrid NAND flash memory devices have been developed, which may be capable of selectively using MLC or SLC memory cells. In particular, some devices may include an SLC memory chip and an MLC memory chip in a single package for performance improvement and cost saving. For example, a device may include both a relatively high-speed and high-priced non-volatile memory (e.g., SLC) and a relatively low-speed and low-priced non-volatile memory (e.g., MLC). In such a device, performance may be affected by a data writing method and a data managing method. In general, a non-volatile memory whose write speed is relatively fast may be frequently updated, and relatively small-size hot data may be recorded in the non-volatile memory. The reduced performance and/or erase count limitations of a non-volatile memory of a relatively slow write speed may be complemented by non-volatile memory of a relatively rapid write speed.
Due to advances in MLC technology, 3-bit and 4-bit MLC memories have been developed. But, problems may arise when the number of bits stored in one memory cell is increased. For example, an erase count of a non-volatile memory may be decreased.
As compared with other memories, flash memory may offer advantages such as a relatively rapid read speed at a relatively low cost. However, an erase operation may be conducted prior to writing data in a flash memory, and a unit of data to be written (or programmed) is typically less than a unit of data to be erased. Such characteristics may make it difficult to use a flash memory as a main memory. Further, such characteristics may obstruct direct use of a file system for hard disk when a flash memory device is used as an auxiliary storage device. Accordingly, a Flash Translation Layer (FTL) may be utilized to provide compatibility between a file system and a flash memory. The FTL may perform a role of mapping a logical address generated by a file system to a physical address of a flash memory to be erased. A representative FTL technique may be a log block mapping technique. The log block mapping technique may be a block mapping method using a limited number of log blocks as a write buffer. The above-described address mapping function of FTL may enable a host to recognize a flash memory as a hard disk drive (or SRAM). This means that a flash memory may be accessed in the same manner as a hard disk drive from the host's perspective.
One function of a FTL may be related to mapping techniques. Examples of mapping techniques are disclosed in U.S. Pat. No. 5,404,485 entitled “FLASH FILE SYSTEM”; U.S. Pat. No. 6,381,176 entitled “METHOD OF DRIVING REMAPPING IN FLASH MEMORY AND FLASH MEMORY ARCHITECTURE SUITABLE THEREFOR”; and U.S. Pat. No. 7,529,879 entitled “INCREMENTAL MERGE METHODS AND MEMORY SYSTEMS USING THE SAME,” the disclosures of which are incorporated by reference herein.